; ;SG 90 サーボ 2 軸 カメラマウントに赤色レーザを搭載し、赤光点を投影する。2018 05 04 ;PIC 12F1572 - I / P ;内臓 16 MHz、0.0625 uS × 4 = 0.25 us / step ;SG 90サーボ ;TowerPro 製 ;寸法 23 × 12．2 × 29 mm、重さ 9 g ;トルク 1．8 kg / cm ( 4．8 V ) ;駆動速度 0．1 sec / 60 deg. (4．8 V ) ;定格電圧 4．8 V ;適正温度 0 - 55 ℃ ;無応答幅（ Dead band width ) 10 μs ;ギア材質 ナイロン ;JR タイプのコネクタはオレンジと赤と茶色のケーブル ;オレンジ ・・・ PWM 信号 ;赤・・・DC 5 V ;茶色・・・GND ;周期・・・20 ms ;DUTY・・・0．5 - 2．4 ms ;左 90 度・・・・・・ 0．5 ms pulse ;ニュートラル 0 ・・・・・ 1．45 ms pulse ;右 90 度・・・・・・ 2．4 ms pulse ;600 us - 2. 2 ms の範囲とする ; ;2 軸ジョイステイック（ 10 KΩ ）を AD 変換する ;AD は、RA 2 の AN 2 と RA 4 の AN 3 を使用 ;充電 15 uS × 2、変換 TAD ( 4 uS ) × 10 = 40 uS ; ;XY マウントは下 X 軸、上 Y 軸とする ;サーボは内臓 PWM モジュール、RA 0 の PWM 2 を X 軸、RA 1 の PWM 1 を Y 軸とする ;PWMCLK は 16 MHｚ、0.0625 us × プリスケーラ 8 = 0.5 us ;周期は 40000 カウントの 20 ms（ 50Hz ） ;DUTY は 5 ms 毎に更新する ; ;ICSP プログラミング ;MCLR､VPP ( RA 3 ) は PB 入力とし 10 KΩ でプルアップ ; ;I/O 割付 ;1 VDD, ICSP VDD target ;2 RA 5, OUT, LED (G) ;3 RA 4, IN, ADC AN 3 ;4 RA 3, IN, 起動ボタン ( 交互停止 ), ICSP Programming voltage ;8 VSS, ICSP VSS ;7 RA 0, OUT, PWM 2, ICSP Data I/O ;6 RA 1, OUT, PWM 1, ICSP Programming Clock ;5 RA 2, IN, ADC AN 2 ; ; LIST P=PIC12F1572 #INCLUDE "p12f1572.inc" ERRORLEVEL -302 ;config 1 ;_FOSC_INTOSC, INTOSC oscillator; I/O function on CLKIN pin ;_WDTE_OFF, WDT disabled ;_PWRTE_ON, PWRT(VDD timer) enabled ;_MCLRE_OFF, MCLR/VPP pin function is digital input ;_CP_OFF, Program memory code protection is disabled ;_BOREN_OFF, Brown-out Reset(VDD drop) disabled ;_CLKOUTEN_OFF, CLKOUT function is disabled. I/O or oscillator function on the CLKOUT pin ;config 2 ;_WRT_OFF, Write protection off ;_STVREN_OFF,Stack Overflow or Underflow will not cause a Reset ;_BORV_LO, Brown-out Reset Voltage (Vbor), low trip point selected. ;_LPBOREN_OFF, LPBOR(Low power BOR)is disabled ;_LVP_OFF, High-voltage on MCLR/VPP must be used for programming __CONFIG _CONFIG1 , _FOSC_INTOSC & _WDTE_OFF & _PWRTE_ON & _MCLRE_OFF & _CP_OFF & _BOREN_OFF & _CLKOUTEN_OFF __CONFIG _CONFIG2 , _WRT_OFF & _STVREN_OFF & _LPBOREN_OFF & _LVP_OFF ;レジスタ定義 ;20H - 6FH 80 bite BANK 0 STARTFLG EQU 20H ;Start flag bit 0 ADX_L EQU 21H ;ADX LOW ADX_H EQU 22H ;ADX HIGH ADY_L EQU 23H ;ADY LOW ADY_H EQU 24H ;ADY HIGH ADS_L EQU 30H ;AD_LOW sub渡し用 ADS_H EQU 31H ;AD_HIGH sub渡し用 AD_L4 EQU 32H ;AD_LOW*4 AD_H4 EQU 33H ;AD_HIGH*4 AD_L12 EQU 34H ;AD_LOW*1/2 AD_H12 EQU 35H ;AD_HIGH*1/2 AD_L14 EQU 36H ;AD_LOW*1/4 AD_H14 EQU 37H ;AD_HIGH*1/4 AD_L18 EQU 38H ;AD_LOW*1/8 AD_H18 EQU 39H ;AD_HIGH*1/8 PRX_L EQU 40H ;Period X_L PRX_H EQU 41H ;Piriod X_H DUTX_L EQU 42H ;Duty X_L DUTX_H EQU 43H ;Duty X_H PRY_L EQU 50H ;Period Y_L PRY_H EQU 51H ;Period Y_H DUTY_L EQU 52H ;Duty Y_L DUTY_H EQU 53H ;Duty Y_H DUT_L EQU 54H ;Duty_L sub渡し用 DUT_H EQU 55H ;Duty_H sub渡し用 T15uSC EQU 60H ;15 us timer T05MSC EQU 61H ;0.5 ms timer T5MSC EQU 62H ;5 ms timer ; ; ;-----Program----- ORG 00H ; CALL INITIAL ; ORG 04H ; GOTO MAIN ; MAIN BANKSEL PORTA ;BANK 0 PBCHK1 ;PB check 1 回目 起動、2 回目 停止の繰り返し BTFSC STARTFLG,0 ;STARTFLG 0 bit = 0 then SKIP GOTO PBCHK6 ;2 回目(停止)検出へ PBCHK2 BTFSC PORTA,RA3 ;PB ON then SKIP 1回目 ( 起動 ) 検出 GOTO MAIN ;MAIN に戻る CALL T5MS ;5 ms CALL T5MS ;5 ms PBCHK3 BTFSC PORTA,RA3 ;PB ON then SKIP GOTO MAIN ;MAIN に戻る PBCHK4 BTFSS PORTA,RA3 ;PB OFF then SKIP GOTO PBCHK4 ;OFFまで待つ CALL T5MS ;5 ms CALL T5MS ;5 ms PBCHK5 BTFSS PORTA,RA3 ;PB OFF then SKIP GOTO PBCHK4 ;OFF まで待つ GOTO RUNSEQ ;起動シーケンスへ PBCHK6 BTFSC PORTA,RA3 ;PB ON then SKIP GOTO RUNSEQ ;起動シーケンスへ CALL T5MS ;5 ms CALL T5MS ;5 ms PBCHK7 BTFSC PORTA,RA3 ;PB ON then SKIP GOTO RUNSEQ ;起動シーケンスへ PBCHK8 BTFSS PORTA,RA3 ;PB OFF then SKIP GOTO PBCHK8 ;OFFまで待つ CALL T5MS ;5 ms CALL T5MS ;5 ms PBCHK9 BTFSS PORTA,RA3 ;PB OFF then SKIP GOTO PBCHK8 ;OFF まで待つ GOTO STOPSEQ ;停止シーケンスへ RUNSEQ ;起動シーケンス BANKSEL PORTA ;BANK 0 BSF STARTFLG,0 ;STARTFLG set CALL T5MS ;5 ms ADX ;X 軸のボリウム値を ADX_L と ADX_H に取込 ;**** X軸 (AN2) **** ;ADCON0: ADC CONTROL REGISTER0 ;bit 7 Unimplemented: Read as '0' ;bit 6-2 CHS<4:0>: Analog Channel Select bits ; 00000 = AN0 ; 00001 = AN1 ; X*00010 = AN2 ; Y*00011 = AN3 ; 00100 = Reserved. No channel connected. ; 11100 = Reserved. No channel connected. ; 11101 = Temperature Indicator(1) ; 11110 = DAC (Digital-to-Analog Converter)(2) ; 11111 = FVR (Fixed Voltage Reference) Buffer 1 Output(3) ;bit 1 GO/DONE: A/D Conversion Status bit GO/DONE ; 1 = A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle. ; This bit is automatically cleared by hardware when the A/D conversion has completed. ; 0 = A/D conversion completed/not in progress ;bit 0 ADON: ADC Enable bit ; *1 = ADC is enabled (charge start) ; 0 = ADC is disabled and consumes no operating current ;Note 1: See Section 14.0 Temperature Indicator Module for more information. ; 2: See Section 16.0 Digital-to-Analog Converter (DAC) Module for more information. ; 3: See Section 13.0 Fixed Voltage Reference (FVR) for more information. BANKSEL ADCON0 ;BANK 1 MOVLW B'00001001' ;AN2, AD ON MOVWF ADCON0 BANKSEL PORTA ;BANK 0 CALL T15uS ;15us wait charge CALL T15uS ;15us wait charge BANKSEL ADCON0 ;BANK 1 BSF ADCON0,1 ;GO / DONE ON BTFSC ADCON0,GO_NOT_DONE ;GO / DONE=0 then SKIP GOTO $-1 ;TAD 4 uS * 10 = 40 us BANKSEL ADRESL ;BANK 1 MOVF ADRESL,W ; BANKSEL PORTA ;BANK 0 MOVWF ADX_L ; BANKSEL ADRESH ;BANK 1 MOVF ADRESH,W ; BANKSEL PORTA ;BANK 0 MOVWF ADX_H ; ADY ;Y 軸の軸のボリウム値を ADY_L と ADY_H に取込 BANKSEL ADCON0 ;BANK 1 MOVLW B'00001101' ;AN 3, AD ON MOVWF ADCON0 ; BANKSEL PORTA ;BANK 0 CALL T15uS ;15 us wait charge CALL T15uS ;15 us wait charge BANKSEL ADCON0 ;BANK 1 BSF ADCON0,1 ;GO / DONE ON BTFSC ADCON0,GO_NOT_DONE ;GO / DONE = 0 then SKIP GOTO $-1 ;TAD 4 uS * 10 = 40 us BANKSEL ADRESL ;BANK 1 MOVF ADRESL,W ; BANKSEL PORTA ;BANK 0 MOVWF ADY_L ; BANKSEL ADRESH ;BANK 1 MOVF ADRESH,W ; BANKSEL PORTA ;BANK 0 MOVWF ADY_H ; ;AD値を DUTYに変換 BANKSEL PORTA ;BANK 0 MOVF ADX_L,W ;X軸_L → W MOVWF ADS_L ;sub 変数に渡す MOVF ADX_H,W ;X軸_H → W MOVWF ADS_H ;sub 変数に渡す CALL ADTODUTY ;ADS_L, ADS_H → DUT_L, DUT_H ;DUTYレジスタに書込 ;X軸 BANKSEL PORTA ;BANK 0 MOVF DUT_L,W ; BANKSEL PWM2DCL ;BANK 27 MOVWF PWM2DCL ;sub 戻値 → X 軸 DUTY_L BANKSEL PORTA ;BANK 0 MOVF DUT_H,W ; BANKSEL PWM2DCH ;BANK 27 MOVWF PWM2DCH ;sub 戻値 → X 軸 DUTY_H BANKSEL PORTA ;BANK 0 MOVF ADY_L,W ;Y 軸_L → W MOVWF ADS_L ;su b変数に渡す MOVF ADY_H,W ;Y 軸_H → W MOVWF ADS_H ;sub 変数に渡す CALL ADTODUTY ;ADS_L, ADS_H → DUT_L, DUT_H ;DUTYレジスタに書込 ;Y軸 BANKSEL PORTA ;BANK 0 MOVF DUT_L,W ; BANKSEL PWM1DCL ;BANK 27 MOVWF PWM1DCL ;sub 戻値 → Y 軸 DUTY_L BANKSEL PORTA ;BANK 0 MOVF DUT_H,W ; BANKSEL PWM1DCH ;BANK 27 MOVWF PWM1DCH ;sub 戻値 → Y 軸 DUTY_H ;LDAセット BANKSEL PWM1LDCON ;BANK 27 BSF PWM1LDCON,LDA ;Armed ON BSF PWM2LDCON,LDA ;Armed ON BANKSEL PORTA ;BANK 0 BSF PORTA,RA5 ;LED ON GOTO MAIN STOPSEQ ;停止シーケンス BANKSEL PORTA ;BANK 0 BCF PORTA,RA5 ;LED OFF BCF STARTFLG,0 ;STARTFLG reset GOTO MAIN ;**** subroutine **** ;**** TIMER FOR 16 MHz 0.25 us / step **** ;15 us T15uS MOVLW 13H ;19,1 MOVWF T15uSC ;1 T15uSLOOP DECFSZ T15uSC,F ;1 * 18 + 2 = 20 GOTO T15uSLOOP ;2 * 18 = 36 RETURN ;2 ;TOTAL 60 * 0.25 us = 15 us ;0.5 ms T05MS MOVLW 0F9H ;249 MOVWF T05MSC NOP NOP NOP NOP NOP T05MSLOOP NOP NOP NOP NOP NOP DECFSZ T05MSC,F GOTO T05MSLOOP RETURN ;TOTAL 2000 * 0.25 us = 500 us = 0.5 ms ;5 ms T5MS MOVLW 0AH ;10,1 MOVWF T5MSC ;1 T5MSLOOP CALL T05MS ; DECFSZ T5MSC,F ;1 * 9 + 2 = 11 GOTO T5MSLOOP ;2 * 9 = 18 RETURN ;2 ;TOTAL 10 * 0.5 ms + 53 * 0.25 us = 5 ms + 13.25 us = 5.01325 ms ;********** AD → DUTYCYCLE ********** ADTODUTY ;ADS_L, ADS_H → DUT_L, DUT_H ; AD servo(us) count 余裕 y = 3.125 x + 1200 ;1024 2400 4800 4400 4400 ;512 1450 2900 **** 2800 ;0 500 1000 1200 1200 ; ;3.125 x = 4 x - x / 2 - x / 4 - x / 8 = 4 x - ( x / 2 + x / 4 + x / 8 ) で計算する ; ;4 倍 BANKSEL PORTA ;BANK 0 MOVF ADS_L,W ;渡されたL値 → 4 倍値Lに仮入れ MOVWF AD_L4 MOVF ADS_H,W ;渡されたH値 → 4 倍値Hに仮入れ MOVWF AD_H4 BCF STATUS,C RLF AD_L4,F ;下位 2 倍 RLF AD_H4,F ;上位 2 倍 BCF STATUS,C RLF AD_L4,F ;下位 2 倍 × 2 倍 = 4 倍 RLF AD_H4,F ;上位 2 倍 × 2 倍 = 4 倍 ;4 倍値 + 1200 ( 04B0H ) → AD_L4,H4 MOVLW 0B0H ;下位 ADDWF AD_L4,F ;AD_L4 + 4CH → AD_L4 MOVLW 04H ;上位 BTFSC STATUS,C ;桁上りなし C = 0 then SKIP MOVLW 05H ADDWF AD_H4,F ;AD_H4 + 04H + (1) → AD_H4 ; ;1 / 2 倍 MOVF ADS_L,W ;渡された L 値 → 1 / 2 倍 L 値に仮入れ MOVWF AD_L12 MOVF ADS_H,W ;渡された H 値 → 1 / 2 倍 H 値に仮入れ MOVWF AD_H12 BCF STATUS,C RRF AD_H12,F ;上位 1 / 2 倍 RRF AD_L12,F ;下位 1 / 2 倍 ;1 / 4 倍 MOVF AD_L12,W ;1 / 2 倍 L 値 → 1 / 4 倍 L 値に仮入れ MOVWF AD_L14 MOVF AD_H12,W ;1 / 2 倍 H 値 → 1 / 4 倍 H 値に仮入れ MOVWF AD_H14 BCF STATUS,C RRF AD_H14,F ;上位 1 / 2 倍 RRF AD_L14,F ;下位 1 / 2 倍 ;1 / 8 倍 MOVF AD_L14,W ;1 / 4 倍 L 値 → 1 / 8 倍 L 値に仮入れ MOVWF AD_L18 MOVF AD_H14,W ;1 / 4 倍 H 値 → 1 / 8 倍 H 値に仮入れ MOVWF AD_H18 BCF STATUS,C RRF AD_H18,F ;上位 1 / 2 倍 RRF AD_L18,F ;下位 1 / 2 倍 ;1 / 2 倍 + 1 / 4 倍 → 1 / 4 倍 MOVF AD_L12,W ;下位 ADDWF AD_L14,F ;AD_L14 + AD_L12 → AD_L14 MOVF AD_H12,W ;上位 BTFSC STATUS,C ;桁上りなし C = 0 then SKIP INCF AD_H12,W ADDWF AD_H14,F ;AD_H14 + + AD_H12 + (1) → AD_H14 ;1 / 4 倍 + 1 / 8 倍 → 1 / 8 倍 MOVF AD_L14,W ;下位 ADDWF AD_L18,F ;AD_L18 + AD_L14 → AD_L18 MOVF AD_H14,W ;上位 BTFSC STATUS,C ;桁上りなし C = 0 then SKIP INCF AD_H14,W ADDWF AD_H18,F ;AD_H18 + + AD_H14 + (1) → AD_H18 ;Total AD_L4, AD_H4 - AD_L18, AD_H18 → AD_L4, AD_H4 → DUT_L, DUT_H MOVF AD_L18,W ;下位 SUBWF AD_L4,F MOVF AD_H18,W ; 上位 BTFSS STATUS,C ;桁借なしC = 1 then SKIP INCF AD_H18,W ; SUBWF AD_H4,F ;AD_H4 - ( AD_H18 + 1 ) MOVF AD_L4,W MOVWF DUT_L MOVF AD_H4,W MOVWF DUT_H RETURN ;********** INITIAL ********** INITIAL ;OSCCON: OSCILLATOR CONTROL REGISTER ;bit 7 SPLLEN: Software PLL Enable bit ; If PLLEN in Configuration Words = 1: ; SPLLEN bit is ignored. 4x PLL is always enabled (subject to oscillator requirements) ; If PLLEN in Configuration Words = 0: ; 1 = 4x PLL Is enabled ; *0 = 4x PLL is disabled ;bit 6-3 IRCF<3:0>: Internal Oscillator Frequency Select bits ; *1111 = 16 MHz HF ; 1110 = 8 MHz or 32 MHz HF (see Section 5.2.2.1 'HFINTOSC') ; 1101 = 4MHz HF ; 1100 = 2MHz HF ; 1011 = 1MHz HF ; 1010 = 500kHz HF(1) ; 1001 = 250kHz HF(1) ; 1000 = 125kHz HF(1) ; 0111 = 500 kHz MF (default upon Reset) ; 0110 = 250kHz MF ; 0101 = 125kHz MF ; 0100 = 62.5kHz MF ; 0011 = 31.25kHz HF(1) ; 0010 = 31.25kHz MF ; 000x = 31kHz LF ;bit 2 Unimplemented: Read as '0' ;bit 1-0 SCS<1:0>: System Clock Select bits ; 1x = Internal oscillator block ; 01 = Timer1 oscillator ; *00 = Clock determined by FOSC<1:0> in Configuration Words. ;Note 1: Duplicate frequency derived from HFINTOSC. ; BANKSEL OSCCON ;BANK 1, POR 0011 1-00 MOVLW B'01111000' ;0_1111_0_00 MOVWF OSCCON ; ;TRISA: PORTA TRI-STATE REGISTER ;bit 7-6 Unimplemented: Read as '0' ;bit 5-4 TRISA<5:4>: PORTA Tri-State Control bit ; 1 = PORTA pin configured as an input (tri-stated) ; 0 = PORTA pin configured as an output ;bit 3 Unimplemented: Read as '1' ;bit 2-0 TRISA<2:0>: PORTA Tri-State Control bit ; 1 = PORTA pin configured as an input (tri-stated) ; 0 = PORTA pin configured as an output ; BANKSEL TRISA ;BANK 1, POR --11 1111 MOVLW B'00011100' ;IN=1 RA2,3,4 MOVWF TRISA ; ;APFCON: ALTERNATE PIN FUNCTION CONTROL REGISTER BANK 2 ; bit 7 RXDTSEL: Pin Selection bit ; 1 = RX/DT function is on RA5 ; 0 = RX/DT function is on RA1 ; bit 6 CWGASEL: Pin Selection bit ; 1 = CWGOUTA function is on RA5 ; 0 = CWGOUTA function is on RA2 ; bit 5 CWGBSEL: Pin Selection bit ; 1 = CWGOUTB function is on RA4 ; 0 = CWGOUTB function is on RA0 ; bit 4 Unimplemented: Read as ‘0’ ; bit 3 T1GSEL: Pin Selection bit ; 1 = T1G function is on RA3 ; 0 = T1G function is on RA4 ; bit 2 TXCKSEL: Pin Selection bit ; 1 = TX/CK function is on RA4 ; 0 = TX/CK function is on RA0 ; bit 1 P2SEL: Pin Selection bit ; 1 = PWM2 function is on RA4 ; *0 = PWM2 function is on RA0 ; bit 0 P1SEL: Pin Selection bit ; 1 = PWM1 function is on RA5 ; *0 = PWM1 function is on RA1 ; ; BANKSEL APFCON ;BANK 2, POR 000-0000 初期設定不要 ; MOVLW B'00000000' ; ; MOVWF APFCON ; ;OPTION_REG: OPTION REGISTER ;bit 7 NOT_WPUEN: Weak Pull-Up Enable bit ; *1 = All weak pull-ups are disabled (except MCLR, if it is enabled) ; 0 = Weak pull-ups are enabled by individual WPUx latch values ;bit 6 INTEDG: Interrupt Edge Select bit ; 1 = Interrupt on rising edge of INT pin ; 0 = Interrupt on falling edge of INT pin ;bit 5 TMR0CS: Timer0 Clock Source Select bit ; 1 = Transition on T0CKI pin ; 0 = Internal instruction cycle clock (FOSC/4) ;bit 4 TMR0SE: Timer0 Source Edge Select bit ; 1 = Increment on high-to-low transition on T0CKI pin ; 0 = Increment on low-to-high transition on T0CKI pin ;bit 3 PSA: Prescaler Assignment bit ; 1 = Prescaler is not assigned to the Timer0 module ; 0 = Prescaler is assigned to the Timer0 module ;bit 2-0 PS<2:0>: Prescaler Rate Select bits ; 000 = 2 ; 001 = 4 ; 010 = 8 ; 011 = 16 ; 100 = 32 ; 101 = 64 ; 110 = 128 ; 111 = 256 ; BANKSEL OPTION_REG ;BANK 1, POR 1111 1111 MOVLW B'10000000' ;NO weak pullup MOVWF OPTION_REG ; ; ;WPUA: WEAK PULL-UP PORTA REGISTER ;bit 7-6 Unimplemented: Read as '0' ;bit 5-0 WPUA<5:0>: Weak Pull-up Register bits(3) ; 1 = Pull-up enabled ; *0 = Pull-up disabled ;Note 1: Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled. ; 2: The weak pull-up device is automatically disabled if the pin is in configured as an output. ; 3: For the WPUA3 bit, when MCLRE = 1, weak pull-up is internally enabled, but not reported here. ; BANKSEL WPUA ;BANK 4, POR --11 1111 MOVLW B'00000000' ;NO weak pullup MOVWF WPUA ; ;AD ;ANSELA: PORTA ANALOG SELECT REGISTER ;bit 7-5 Unimplemented: Read as '0' ;bit 4 ANSA4: Analog Select between Analog or Digital Function on pins RA4, respectively ; *1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled. ; 0 = Digital I/O. Pin is assigned to port or digital special function. ;bit 3 Unimplemented: Read as '0' ;bit 2-0 ANSA<2:0>: Analog Select between Analog or Digital Function on pins RA<2:0>, respectively ; 1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled. ; 0 = Digital I/O. Pin is assigned to port or digital special function. ;Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to ; allow external control of the voltage on the pin. ; BANKSEL ANSELA ;BANK 3, POR ---1 -111 MOVLW B'00010100' ;RA2,RA4 analog input MOVWF ANSELA ; ;ADCON1: A/D CONTROL REGISTER 1 ;bit 7 ADFM: A/D Result Format Select bit ; *1 = Right justified. Six Most Significant bits of ADRESH are set to '0' when the conversion result is loaded. ; 0 = Left justified. Six Least Significant bits of ADRESL are set to '0' when the conversion result is loaded. ;bit 6-4 ADCS<2:0>: A/D Conversion Clock Select bits ; 000 = FOSC/2 ; 001 = FOSC/8 ; 010 = FOSC/32, TAD 2us 16MHz ; 011 = FRC (clock supplied from a dedicated RC oscillator) ; 100 = FOSC/4 ; 101 = FOSC/16, TAD 1us 16MHz ; *110 = FOSC/64, TAD 4us 16MHz ; 111 = FRC (clock supplied from a dedicated RC oscillator) ;bit 3-2 Unimplemented: Read as '0' ;bit 1-0 ADPREF<1:0>: A/D Positive Voltage Reference Configuration bits ; *00 = VREF+ is connected to VDD ; 01 = Reserved ; 10 = VREF+ is connected to external VREF+ pin(1) ; 11 = Reserved ;Note 1: When selecting the VREF+ pin as the source of the positive reference, be aware that a minimum voltage ; specification exists. See Section 27.0 Electrical Specifications for details. ; BANKSEL ADCON1 ;BANK 1, POR 0000 --00 MOVLW B'11100000' MOVWF ADCON1 ; ;ADCON2: A/D CONTROL REGISTER 2 ;bit 7-4 TRIGSEL<3:0>: Auto-Conversion Trigger Selection bits(1) ; *0000 = No auto-conversion trigger selected ; 0001 = PWM1 - PWM1_interrupt ; 0010 = PWM2 - PWM2_interrupt ; 0011 = Timer0 - T0_overflow(2) ; 0100 = Timer1 - T1_overflow(2) ; 0101 = Timer2 - T2_match ; 0110 = Comparator C1 - C1OUT_sync ; 0111 = PWM3 - PWM3_interrupt ; 1000 = PWM1 - PWM1_OF1_match ; 1001 = PWM2 - PWM2_OF2_match ; 1010 = PWM3 - PWM3_OF3_match ; 1011 = Reserved ; 1100 = Reserved ; 1101 = Reserved ; 1110 = Reserved ; 1111 = Reserved ; bit 3-0 Unimplemented: Read as '0' ; Note 1: This is a rising edge sensitive input for all sources ; 2: Signal also sets its corresponding interrupt flag ; BANKSEL ADCON2 ;BANK 1, POR 0000 ---- MOVLW B'00000000' ; MOVWF ADCON2 ; ;PWM ;PWMxCON: PWMx CONTROL REGISTER 22-1 ; bit 7 EN: PWMx Module Enable bit ; *1 = Module is enabled ; 0 = Module is disabled ; bit 6 OE: PWMx Output Enable bit ; *1 = PWM output pin enabled ; 0 = PWM output pin disabled ; bit 5 OUT: Output state of the PWM module bit ; bit 4 POL: PWMx Output Polarity Control bit ; 1 = PWM output active state is low ; *0 = PWM output active state is high ; bit 3-2 MODE<1:0>: PWMx Mode Control bit ; 11 = Center Aligned mode ; 10 = Toggle On Match mode ; 01 = Set On Match mode ; *00 = Standard PWM mode ; bit 1-0 Unimplemented: Read as '0’ ; BANKSEL PWM1CON ;BANK 27,POR 0000 00-- MOVLW B'11000000' MOVWF PWM1CON MOVWF PWM2CON ; ;PWMxINTE: PWMx INTERRUPT ENABLE REGISTER 22-2 ; bit 7-4 Unimplemented: Read as ‘0’ ; bit 3 OFIE: Offset Interrupt Enable bit ; 1 = Interrupts CPU on offset match ; 0 = Does not interrupt CPU on offset match ; bit 2 PHIE: Phase Interrupt Enable bit ; 1 = Interrupts CPU on phase match ; 0 = Does not Interrupt CPU on phase match ; bit 1 DCIE: Duty Cycle Interrupt Enable bit ; 1 = Interrupts CPU on duty cycle match ; 0 = Does not interrupt CPU on duty cycle match ; bit 0 PRIE: Period Interrupt Enable bit ; 1 = Interrupts CPU on period match ; 0 = Does not interrupt CPU on period match ; BANKSEL PWM1INTE ;BANK 27,POR ---- 000 MOVLW B'00000000' MOVWF PWM1INTE MOVWF PWM2INTE ; ;PWMxINTF: PWMx INTERRUPT REQUEST REGISTER 22-3 ; bit 7-4 Unimplemented: Read as ‘0’ ; bit 3 OFIF: Offset Interrupt Flag bit(1) ; 1 = Offset match event occurred ; 0 = Offset match event did not occur ; bit 2 PHIF: Phase Interrupt Flag bit(1) ; 1 = Phase match event occurred ; 0 = Phase match event did not occur ; bit 1 DCIF: Duty Cycle Interrupt Flag bit(1) ; 1 = Duty cycle match event occurred ; 0 = Duty cycle match event did not occur ; bit 0 PRIF: Period Interrupt Flag bit(1) ; 1 = Period match event occurred ; 0 = Period match event did not occur ; Note 1: Bit is forced clear by hardware while module is disabled (EN = 0). ; BANKSEL PWM1INTF ;BANK 27,POR ---- 000 MOVLW B'00000000' MOVWF PWM1INTF MOVWF PWM2INTF ; ;PWMxCLKCON: PWMx CLOCK CONTROL REGISTER 22-4 ;bit 7 Unimplemented: Read as '0’ ; 6-4 PS<2:0>: Clock Source Prescaler Select bits ; 111 = Divide clock source by 128 ; 110 = Divide clock source by 64 ; 101 = Divide clock source by 32 ; 100 = Divide clock source by 16 ; *011 = Divide clock source by 8 -- Tosc 0.0625us X 8 = 0.5us ; 010 = Divide clock source by 4 ; 001 = Divide clock source by 2 ; 000 = No Prescaler ;bit 3-2 Unimplemented: Read as '0’ ;bit 1-0 CS<1:0>: Clock Source Select bits ; 11 = Reserved ; 10 = LFINTOSC ; *01 = HFINTOSC ; 00 = FOSC ; BANKSEL PWM1CLKCON ;BANK 27, POR -000 -000 MOVLW B'00110001' MOVWF PWM1CLKCON MOVWF PWM2CLKCON ; ;PWMxLDCON: PWMx RELOAD TRIGGER SOURCE SELECT REGISTER 22-5 ; bit 7 LDA: Load Buffer Armed bit(1) ; If LDT = 1: ; 1 = Loads the OFx, PHx, DCx and PRx buffers at the end of the period when the selected trigger occurs ; 0 = Does not load buffers or load has completed ; If LDT = 0: ; *1 = Loads the OFx, PHx, DCx and PRx buffers at the end of the current period ; 0 = Does not load buffers or load has completed ; bit 6 LDT: Load Buffer on Trigger bit ; 1 = Loads buffers on trigger enabled ; *0 = Loads buffers on trigger disabled ; Loads the OFx, PHx, DCx and PRx buffers at the end of every period after the selected trigger occurs. ; Reloads internal double buffers at the end of current period. The LDS<1:0> bits are ignored. ; bit 5-2 Unimplemented: Read as ‘0’ ; bit 1-0 LDS<1:0>: Load Trigger Source Select bits ; 11 = LD3_trigger(2) ; 10 = LD2_trigger(2) ; 01 = LD1_trigger(2) ; 00 = Reserved ; Note 1: This bit is cleared by the module after a reload operation ; It can be cleared in software to clear an existing arming event ; 2: The LD_trigger corresponding to the PWM used becomes reserved ; BANKSEL PWM1LDCON ;BANK 27, POR -000 -000 MOVLW B'10000000' MOVWF PWM1LDCON MOVWF PWM2LDCON ; ;PWMxOFCON: PWMx OFFSET TRIGGER SOURCE SELECT REGISTER 22-6 ; bit 7 Unimplemented: Read as ‘0’ ; bit 6-5 OFM<1:0>: Offset Mode Select bits ; 11 = Continuous Slave Run mode with immediate Reset and synchronized start when the selected offset trigger occurs ; 10 = One-Shot Slave Run mode with synchronized start when the selected offset trigger occurs ; 01 = Independent Slave Run mode with synchronized start when the selected offset trigger occurs ; *00 = Independent Run mode ; bit 4 OFO: Offset Match Output Control bit(1) ; If MODE<1:0> = 11 (PWM Center-Aligned mode): ; 1 = OFx_match occurs on counter match when counter decrementing, (second match) ; 0 = OFx_match occurs on counter match when counter incrementing, (first match) ; If MODE<1:0> = 00, 01 or 10 (all other modes): Bit is ignored. ; bit 3-2 Unimplemented: Read as ‘0’ ; bit 1-0 OFS<1:0>: Offset Trigger Source Select bits ; 11 = OF3_match(1) ; 10 = OF2_match(1) ; 01 = OF1_match(1) ; *00 = Reserved ; Note 1: The OFx_match corresponding to the PWM used becomes reserv ; BANKSEL PWM1OFCON ;BANK 27, POR -000 -000 MOVLW B'00000000' MOVWF PWM1OFCON MOVWF PWM2OFCON ; ;PWMxPHH: PWMx PHASE COUNT HIGH REGISTER 22-7 ; bit 7-0 PH<15:8>: PWMx Phase High bits ; Upper eight bits of PWM phase count ; BANKSEL PWM1PHH ;BANK 27, POR xxxx xxxx MOVLW B'00000000' ;PHASE 0 MOVWF PWM1PHH MOVWF PWM2PHH ; ;PWMxPHL: PWMx PHASE COUNT LOW REGISTER 22-8 ; bit 7-0 PH<7:0>: PWMx Phase Low bits ; Lower eight bits of PWM phase count ; BANKSEL PWM1PHL ;BANK 27, POR xxxx xxxx MOVLW B'00000000' ;PHASE 0 MOVWF PWM1PHL MOVWF PWM2PHL ; ; ;PWMxDCH: PWMx DUTY CYCLE COUNT HIGH REGISTER 22-9 ; bit 7-0 DC<15:8>: PWMx Duty Cycle High bits ; Upper eight bits of PWM duty cycle count ; BANKSEL PWM1DCH ;BANK 27, POR xxxx xxxx MOVLW 0AH ;2800=0AF0H MOVWF PWM1DCH MOVWF PWM2DCH ; ;PWMxDCL: PWMx DUTY CYCLE COUNT LOW REGISTER 22-10 ; bit 7-0 DC<7:0>: PWMx Duty Cycle Low bits ; Lower eight bits of PWM duty cycle count ; BANKSEL PWM1DCL ;BANK 27, POR xxxx xxxx MOVLW 0F0H ;2800=0AF0 MOVWF PWM1DCL MOVWF PWM2DCL ; ;PWMxPRH:PWMx PERIOD COUNT HIGH REGISTER 22-11 ;bit 7-0 PR<15:8> PWM Period High bits ;Upper eight bits of PWM period count ;20 ms = 0.5us * 40000 (9C40H) ; BANKSEL PWM1PRH ;BANK 27, POR xxxx xxxx MOVLW 9CH MOVWF PWM1PRH MOVWF PWM2PRH ; ;PWMxPRL:PWMx PERIOD COUNT LOW REGISTER 22-12 ;bit 7-0 PR<15:8>: PWM Period Low bits ; Lower eight bits of PWM period count. ; 20 ms =0.5us * 40000 (9C40H) ; BANKSEL PWM1PRL ;BANK 27, POR xxxx xxxx MOVLW 40H MOVWF PWM1PRL MOVWF PWM2PRL ; ;PWMxOFH: PWMx OFFSET COUNT HIGH REGISTER 22-13 ; bit 7-0 OF<15:8>: PWMx Offset High bits ; Upper eight bits of PWM offset count. ; BANKSEL PWM1OFH ;BANK 27, POR xxxx xxxx MOVLW 00H MOVWF PWM1OFH MOVWF PWM2OFH ; ;PWMxOFL: PWMx OFFSET COUNT LOW REGISTER 22-14 ;bit 7-0 OF<7:0>: PWMx Offset Low bits ; Lower eight bits of PWM offset count. ; BANKSEL PWM1OFL ;BANK 27, POR xxxx xxxx MOVLW 00H MOVWF PWM1OFL MOVWF PWM2OFL ; ;PWMxTMRH: PWMx TIMER HIGH REGISTER 22-15(状態表示) ; bit 7-0 TMR<15:8>: PWMx Timer High bits ; Upper eight bits of PWM timer counter ; ; BANKSEL PWM1TMRH ;BANK 27, POR xxxx xxxx ; ;PWMxTMRL: PWMx TIMER LOW REGISTER 22-16(状態表示) ; bit 7-0 TMR<15:8>: PWMx Timer Low bits ; Lower eight bits of PWM timer counter ; ; BANKSEL PWM1TMRL ;BANK 27, POR xxxx xxxx ; ; ;PWMEN: PWMEN BIT ACCESS REGISTER 22-17(状態表示) ; bit 7-3 Unimplemented: Read as ‘0’ ; bit 2-0 PWMxEN_A: PWM3/PWM2/PWM1 Enable bits ; Mirror copy of EN bits in PWMxCON<7> ; ; BANKSEL PWMEN ;BANK 27, POR ---- -000 ; ;PWMLD: LD BIT ACCESS REGISTER 22-18(状態表示) ; bit 7-3 Unimplemented: Read as ‘0’ ; bit 2-0 PWMxLDA_A: PWM3/PWM2/PWM1 LD bits ; Mirror copy of LD bits in PWMxLDCON<7> ; ; BANKSEL PWMLD ;BANK 27, POR ---- -000 ; ;PWMOUT: PWMOUT BIT ACCESS REGISTER 22-19(状態表示) ; bit 7-3 Unimplemented: Read as ‘0’ ; bit 2-0 PWMxOUT_A: PWM3/PWM2/PWM1 Output bits ; Mirror copy of OUT bits in PWMxCON<5> ; ; BANKSEL PWMOUT ;BANK 27, POR ---- -000 ; ; ;レジスタ類リセット BANKSEL PORTA ;BANK=0 CLRF STARTFLG ;Start flag CLRF ADX_L ;ADX_L CLRF ADX_H ;ADX_H CLRF ADY_L ;ADY_L CLRF ADY_H ;ADY_H CLRF ADS_L ;ADS_L CLRF ADS_H ;ADS_H CLRF PRX_L ;Period X_L CLRF PRX_H ;Piriod X_H CLRF DUTX_L ;Duty X_L CLRF DUTX_H ;Duty X_H CLRF PRY_L ;Period Y_L CLRF PRY_H ;Piriod Y_H CLRF DUTY_L ;Duty Y_L CLRF DUTY_H ;Duty Y_H BCF PORTA,RA5 ;LED OFF RETURN END